■ 邀請國外學者Dr. Jeffrey Draper進行演講
演講時間：2012.12.12 下午 15:30-16:30
Title of Talk：
Enabling Techniques for Extreme-Scale Computing
Dr. Jeffrey Draper
USC Information Sciences Institute
Abstract of Talk：
Extreme-scale computing to date has progressed from giga to tera to peta over the last 25 years due largely in advances simply stemming from riding the Moore’s Law curve. However, several studies have shown that analogous to the power wall that caused processor design to shift to multi-core, there are many barriers that will prevent achieving exascale class systems if we simply rely on technology trends. The most significant challenges include energy efficiency, resilience, and managing massive amounts of concurrency. Dr. Draper’s MARINA research group at USC has been investigating several techniques for making advances in energy-efficient extreme-scale memory-oriented computing using an underlying 3DIC technology with transactional memory architectural concepts. This talk will present the latest results from the ongoing research conducted in these areas.
Brief Biography of Speaker：
Dr. Jeffrey Draper holds a joint appointment as a Research Associate Professor in the Ming Hsieh Department of Electrical Engineering and Project Leader at Information Sciences Institute in the Viterbi School of Engineering at the University of Southern California. Dr. Draper has led the micro-architecture and/or VLSI effort on several large projects in the past 15 years, including many DARPA-sponsored programs such as Integrity and Reliability in Integrated Circuits, Ubiquitous High-Performance Computing, Trust in Integrated Circuits, Radiation Hardening by Design, Polymorphous Computing Architectures, and Data-Intensive Systems. In the past few years, his research group has fabricated several chips in IBM 32nm, 65nm, and 90nm technology, including SOC and quadcore processors and two radiation-tolerant SRAM chips. Additionally, his group contributed to the architecture and VLSI implementation of the MONARCH chip in IBM 90nm technology, a 100M-gate chip containing 6 RISC processors with multimedia extension units, 12 MB of embedded DRAM, a streaming computing fabric, two external DDR DRAM memory ports, two Rapid I/O ports, and sixteen high-speed serial ports. Prior to this work, Dr. Draper's group completed the design and implementation of two generations of processing-in-memory (PIM) chips for the Data-Intensive Architecture (DIVA) project. Dr. Draper graduated summa cum laude with a BS in Electrical Engineering from Texas A & M University and an MSE and PhD in Computer Engineering from the University of Texas at Austin. His research interests are energy-efficient memory-oriented architectures including transactional memory, resilience, 3DIC, and networks on chip. He has authored or co-authored over 100 papers on many aspects of computer architecture and VLSI. Dr. Draper is an IEEE Senior Member.